Build date: 1775512803 - Mon Apr  6 22:00:03 UTC 2026
Build cvs date: 1775504887 - Mon Apr  6 19:48:07 UTC 2026
Build id: 2026-04-07.1
Build tags: amd64-regress ports sysupgrade

Applied the following diff(s):
/home/anton/tmp/robsd/src-sys-em.diff
/home/anton/tmp/robsd/src-sys-uhidev-sispm.diff
/home/anton/tmp/robsd/src-sysupgrade.diff

P distrib/sets/lists/man/mi
P lib/libcrypto/cms/cms_local.h
P lib/libcrypto/x509/x509v3.h
P share/man/man4/man4.riscv64/Makefile
U share/man/man4/man4.riscv64/smtclock.4
U share/man/man4/man4.riscv64/smtcomphy.4
U share/man/man4/man4.riscv64/smtiic.4
P share/man/man4/man4.riscv64/stfclock.4
P sys/arch/amd64/amd64/pmap.c
P sys/arch/loongson/conf/files.loongson
P sys/arch/loongson/dev/apm.c
P sys/arch/loongson/include/apmvar.h
cvs server: sys/arch/loongson/include/hibernate.h is no longer in the repository
cvs server: sys/arch/loongson/include/hibernate_var.h is no longer in the repository
P sys/arch/loongson/loongson/autoconf.c
cvs server: sys/arch/loongson/loongson/hibernate_machdep.c is no longer in the repository
P sys/arch/loongson/loongson/locore.S
P sys/arch/loongson/loongson/loongson2_machdep.c
P sys/arch/loongson/loongson/loongson3_machdep.c
P sys/arch/loongson/loongson/machdep.c
P sys/arch/riscv64/conf/GENERIC
P sys/arch/riscv64/conf/RAMDISK
P sys/arch/riscv64/conf/files.riscv64
P sys/arch/riscv64/dev/smtclock.c
U sys/arch/riscv64/dev/smtiic.c
U sys/arch/riscv64/dev/smtpmic.c
P sys/arch/riscv64/include/cpu.h
P sys/arch/riscv64/riscv64/cpu.c
P sys/arch/riscv64/riscv64/trap.c
P sys/arch/riscv64/stand/efiboot/conf.c
P sys/arch/riscv64/stand/efiboot/efiboot.c
P sys/dev/fdt/com_fdt.c
P sys/dev/ic/com.c
P sys/dev/ic/comvar.h
P sys/dev/pci/pcidevs
P sys/dev/pci/pcidevs.h
P sys/dev/pci/pcidevs_data.h
M sys/dev/usb/uhidev.c
P usr.bin/less/tags.c
M usr.sbin/bgpd/session.c
P usr.sbin/relayd/parse.y

commit xl8KF1S8yE7y5iU6
Author: kettenis
Date: 2026/04/06 19:48:07

  Add smtpmic(4), a driver for the SpacemiT P1 PMIC.

  ok jca@, mlarkin@

  sys/arch/riscv64/conf/GENERIC
  sys/arch/riscv64/conf/RAMDISK
  sys/arch/riscv64/conf/files.riscv64
  sys/arch/riscv64/dev/smtpmic.c

commit THFqDRlsTr1fOWqi
Author: mlarkin
Date: 2026/04/06 19:34:08

  remove incomplete/never finished loongson hibernate code

  This was started many years ago and never finished. Ongoing work in hibernate
  is complicated by having this old code present.

  ok miod

  sys/arch/loongson/conf/files.loongson
  sys/arch/loongson/dev/apm.c
  sys/arch/loongson/include/apmvar.h
  sys/arch/loongson/loongson/autoconf.c
  sys/arch/loongson/loongson/locore.S
  sys/arch/loongson/loongson/loongson2_machdep.c
  sys/arch/loongson/loongson/loongson3_machdep.c
  sys/arch/loongson/loongson/machdep.c

commit wKC4e1mokZNyB1rp
Author: kettenis
Date: 2026/04/06 19:12:36

  Sadly the SpacemiT K1 has peripherals than can only do 32-bit DMA.

  ok jca@, mlarkin@, deraadt@

  sys/arch/riscv64/stand/efiboot/conf.c
  sys/arch/riscv64/stand/efiboot/efiboot.c

commit W0poDphg4Uh4HvAX
Author: mlarkin
Date: 2026/04/06 18:27:33

  zero direct map pages before populating

  Zero the DM PTE/PDE pages before use. Fixes a bug on machines with more than
  512GB RAM; those pages might contain previous data/junk and panic during
  pmap_randomize.

  Tested on various amd64 laptops, an openbsd amd64 vmm VM and an EPYC server
  with 1TB RAM.

  Fix supplied by Chris Cunningham, thanks!

  sys/arch/amd64/amd64/pmap.c

commit 6rdZZLxIX3BIPfCw
Author: deraadt
Date: 2026/04/06 17:58:33

  sync

  distrib/sets/lists/man/mi

commit IFQTcsQ9LVZLzJhr
Author: kettenis
Date: 2026/04/06 10:50:59

  smtcomphy(4)

  share/man/man4/man4.riscv64/Makefile
  share/man/man4/man4.riscv64/smtcomphy.4

commit pcdOVljseGxA6jjd
Author: kettenis
Date: 2026/04/06 10:46:13

  smtiic(4)

  share/man/man4/man4.riscv64/Makefile
  share/man/man4/man4.riscv64/smtiic.4

commit 27UXKW0K4xeXTTeW
Author: kettenis
Date: 2026/04/06 10:42:12

  smtclock(4)

  share/man/man4/man4.riscv64/Makefile
  share/man/man4/man4.riscv64/smtclock.4

commit hzG2URf8PT01wskl
Author: kettenis
Date: 2026/04/06 10:41:31

  Fix pasto.

  share/man/man4/man4.riscv64/stfclock.4

commit 7ont8hhxroTN9Rkx
Author: kettenis
Date: 2026/04/06 10:30:27

  Add smtiic(4), a driver for the I2C controller found on the SpacemiT K1
  SoC.  This is a close relative of mviic(4), but the register layout
  changed and some bits moved within the registers.

  ok jca@

  sys/arch/riscv64/conf/GENERIC
  sys/arch/riscv64/conf/RAMDISK
  sys/arch/riscv64/conf/files.riscv64
  sys/arch/riscv64/dev/smtclock.c
  sys/arch/riscv64/dev/smtiic.c

commit 4orGLjUGxtceUZHm
Author: kettenis
Date: 2026/04/06 10:27:53

  Bring back the PXA2X0 variant; it resurfaced in the SpacemiT K1 SoC.
  Incorporate a fix inspired by NetBSD to keep the console enabled when
  userland closes the device.

  sys/dev/fdt/com_fdt.c
  sys/dev/ic/com.c
  sys/dev/ic/comvar.h

commit JL586Lo8EOFow0tH
Author: kirill
Date: 2026/04/06 09:14:54

  relayd: support TLS with multiple listeners

  Fix a bug in relay_inherit() which runs only
  relay_load_certfiles(conf, rb, NULL) unconditionally which isn't
  alligned with logic in parser when it parses relay block, where multiple
  certificates are load as relay_load_certfiles(conf, rb, NULL) only if
  here no tlscerts (for default host) and otherwise it loads keypairs.

  OK: rsadowski@

  usr.sbin/relayd/parse.y

commit tXnPoxnfY8M4YgyW
Author: tb
Date: 2026/04/06 08:24:57

  x509v3.h: remove pointless #ifdef HEADER_CONF_H

  x509v3.h has included conf.h since June 20, 1999, OpenSSL commit ba404b5e,
  so HEADER_CONF_H has been defined since then. Also since then, CONF_VALUE
  (only available via conf.h) has been used outside of HEADER_CONF_H, making
  that #ifdef doubly pointless.

  ok bcook jsing kenjiro

  lib/libcrypto/x509/x509v3.h

commit DGv7pdlX11tGa124
Author: tb
Date: 2026/04/06 08:18:19

  cms_local.h: remove #ifdef X509V3_HEADER_H

  All thirteen files including cms_local.h do that after including cms.h,
  which already includes x509v3.h, so this is always defined. While here
  make the cms_local.h a bit more selfstanding by including asn1.h and
  x509v3.h

  ok bcook jsing (who had the same diff) kenjiro

  lib/libcrypto/cms/cms_local.h

commit lhAvuT3JcYbLteXb
Author: jca
Date: 2026/04/06 08:13:22

  Tweak vendor #define list to follow numerical ordering

  No functional change

  sys/arch/riscv64/riscv64/cpu.c

commit WkDQTFqF4QxR1Aw1
Author: jca
Date: 2026/04/06 08:10:54

  Follow the sparc64 lead and simply define curcpu in the kernel as the
  special register containing its value, this is a general register (x4)
  and therefore can be used directly

  Diff stolen from miod@ who is on strike but agreed to let me commit
  this.  ok kettenis@

  sys/arch/riscv64/include/cpu.h

commit BCesPpuPYDguBlmS
Author: op
Date: 2026/04/05 23:17:30

  fix crash on invalid tags file

  If the tag entry points to the line number zero, less crashes because
  internally it uses that line number to imply that the tag is associated
  with a pattern.

  issue reported by Henry Ford (henryfordkjv at gmail), thanks!

  ok kirill@

  usr.bin/less/tags.c

commit OeszMGPbKmJH5TG2
Author: kettenis
Date: 2026/04/05 22:13:21

  Treat "Instruction access fault" (EXCP_FAULT_FETCH) traps as PROT_EXEC.
  Fixes random SIGSEGV on the SpecemiT X60 cores.

  ok mlarkin@, deraadt@

  sys/arch/riscv64/riscv64/trap.c

commit kbkspEIdQmi07ytb
Author: kettenis
Date: 2026/04/05 22:09:58

  regen

  sys/dev/pci/pcidevs.h
  sys/dev/pci/pcidevs_data.h

commit 7mhDgMUiIKGbk5gv
Author: kettenis
Date: 2026/04/05 22:06:19

  Add SpacemiT K1.

  sys/dev/pci/pcidevs