Build date: 1775426403 - Sun Apr  5 22:00:03 UTC 2026
Build cvs date: 1775412491 - Sun Apr  5 18:08:11 UTC 2026
Build id: 2026-04-06.1
Build tags: amd64-regress ports sysupgrade

Applied the following diff(s):
/home/anton/tmp/robsd/src-sys-em.diff
/home/anton/tmp/robsd/src-sys-uhidev-sispm.diff
/home/anton/tmp/robsd/src-sysupgrade.diff

P sys/arch/loongson/loongson/machdep.c
P sys/arch/mips64/mips64/cpu.c
P sys/arch/octeon/octeon/machdep.c
P sys/arch/riscv64/conf/GENERIC
P sys/arch/riscv64/conf/RAMDISK
P sys/arch/riscv64/conf/files.riscv64
P sys/arch/riscv64/dev/sfcc.c
U sys/arch/riscv64/dev/smtclock.c
U sys/arch/riscv64/dev/smtcomphy.c
P sys/arch/riscv64/include/cpufunc.h
P sys/arch/riscv64/include/pmap.h
P sys/arch/riscv64/include/pte.h
P sys/arch/riscv64/riscv64/bus_dma.c
P sys/arch/riscv64/riscv64/cpu.c
P sys/arch/riscv64/riscv64/pmap.c
M sys/dev/usb/uhidev.c
P usr.bin/tmux/format.c
P usr.bin/tmux/grid.c
P usr.bin/tmux/screen.c
P usr.bin/tmux/tmux.h
P usr.bin/tmux/tty-features.c
M usr.sbin/bgpd/session.c

commit FDhAHYfCTUR6OWwr
Author: kettenis
Date: 2026/04/05 18:08:11

  Add smtcomphy(4), a driver for the USB3/PCIe combo PHY found on the
  SpacemiT K1 SoC.

  ok jsing@, jca@

  sys/arch/riscv64/conf/GENERIC
  sys/arch/riscv64/conf/RAMDISK
  sys/arch/riscv64/conf/files.riscv64
  sys/arch/riscv64/dev/smtcomphy.c

commit jaSZi3JsOdvBBf0q
Author: nicm
Date: 2026/04/05 15:43:17

  When a cell is cleared after having been moved, we cannot reuse its
  extended data, because that may still be in use. Add a flag to
  grid_clear_cell to indicate this. Fixes irritating problems with ICH
  (CSI @) mostly visible in emacs.

  usr.bin/tmux/grid.c
  usr.bin/tmux/screen.c
  usr.bin/tmux/tmux.h

commit Xwz6cgS1gyKCaiv5
Author: nicm
Date: 2026/04/05 14:29:04

  Add extkeys feature to tmux itself so nested tmux works, GitHub issue 4960.

  usr.bin/tmux/tty-features.c

commit fBuaWnYgtWcK21UZ
Author: nicm
Date: 2026/04/05 13:24:02

  Set less crazy limits (than INT_MAX) for pad and trim, makes ossfuzz happier.

  usr.bin/tmux/format.c

commit Np9EHJeXIgZTnchO
Author: kn
Date: 2026/04/05 13:11:58

  Hoist mips64 CPU accounting to get multiple softnet threads on MP systems

  Increment ncpus (hw.ncpu) in mips64 cpuattach() instead of octeon/loongson
  hw_cpu_hatch() running before, not after MI sofnet_percpu(), respectively.

  This matches what arm64, macppc and powerpc64 do.

  Local traffic may now be distributed across multiple threads, while physical
  drivers like cnmac(4/octeon) still lack multiqueue support to do so.

  loongson was not tested, but should behave the same.

  initial report Jordan Geoghegan
  tests kirill bluhm Janne Johansson
  feedback miod bluhm kettenis
  OK kirill visa

  sys/arch/loongson/loongson/machdep.c
  sys/arch/mips64/mips64/cpu.c
  sys/arch/octeon/octeon/machdep.c

commit yLn2Zp6BSLOeTFmV
Author: kettenis
Date: 2026/04/05 11:48:17

  Implement support for the Zicbom and Svpbmt extensions.  Rework the cache
  flushing code to operate on virtual addresses instead of physical
  addresses.  Seems the Zicbom implementation on the SpacemiT X60 cores
  doesn't flush the caches if the mapping is non-cachable.  So adjust
  _pmap_kenter_pa() to use a temporary cachable mapping to clean a page we
  want to map non-cachable.

  ok jca@

  sys/arch/riscv64/dev/sfcc.c
  sys/arch/riscv64/include/cpufunc.h
  sys/arch/riscv64/include/pmap.h
  sys/arch/riscv64/include/pte.h
  sys/arch/riscv64/riscv64/bus_dma.c
  sys/arch/riscv64/riscv64/cpu.c
  sys/arch/riscv64/riscv64/pmap.c

commit Lvl6WxLyAClwZJp4
Author: kettenis
Date: 2026/04/05 11:40:50

  Add smtclock(4), a driver for the clock/reset controller on the SpacemiT
  K1 SoC.

  ok jca@

  sys/arch/riscv64/conf/GENERIC
  sys/arch/riscv64/conf/RAMDISK
  sys/arch/riscv64/conf/files.riscv64
  sys/arch/riscv64/dev/smtclock.c